In conventional data transmission systems, a frame of data may contain several messages with indeterministic length. Usually, a message contains a header and a data block. The length of the data block can be obtained by decoding one or more bits in the header. In order to process each message, the header is processed first. After decoding the header information, such as the message type and length, the data block can be read and processed.
Referring to FIG. 1, an example of a frame 10 illustrating several messages is shown. The messages of the frame 10 have an indeterministic length illustrated as the data blocks 12a-12n. A number of headers 14a-14n are shown before each of the data blocks 12a-12n. A cyclical redundancy check (CRC) section 16 is shown after the last data block 12n. 
The location of the first bit of the first header 14a is known. Normally, the header 14a starts at the MSB (most significant bit) of the first word, or at the LSB (least significant bit) of the first word. Since the length of the first data block 12a is indeterministic, the first bit of the next header (e.g., 14b) can start anywhere within a word. For example, if the data is supplied as 16-bit words, and the first message length (i.e., one header and one data block) is 274 bits, the next header will start at bit 14 (when the header starts at the MSB) or bit 3 (when the header starts at the LSB). Using conventional approaches, the header starts from a known location to be decoded. After decoding the header, the data block can be processed.
When the data of a message within a frame is read and processed by software, the data is first shifted so the header is in a known location. The software can then decode the header, get the length and other information, and process the data. Implementing a similar method in hardware uses a shift register and associated control logic.
Processing messages with indeterministic length using conventional approaches uses a large amount of shifting and preprocessing. Such shifting and preprocessing increases the processing consumption (e.g., millions of instructions per second, or MIPS) and can create problems, especially when the data rate is high and the frame size is large.
It would be desirable to implement in hardware, a method and/or apparatus to adjust the data messages that minimizes shift operations.